Design of cost-efficient interconnect processing units

Design of cost-efficient interconnect processing units

Spidergon STNoC

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Streamlined Design Solutions Specifically for NoCTo solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of l.

Format
288 pages, Hardcover
First published
2009
Publishers
Taylor & Francis
Subjects
St microelectronics·Networks on a chip·Microprocessors
Language
English

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